1. Field of the Invention.
The invention relates to the field of the chemical-mechanical polishing of semiconductor wafers.
2. Prior Art and Related Art.
In semiconductor processing rough or undulation layers, or abrupt changes in contours are avoided. These layers and contours can cause high stress, cracking and electromigration in metal layers, and optical aberrations, among other problems.
One early technique for eliminating the abrupt contours in a glass layer resulting from etching contact openings was to reflow the glass layer as taught by U.S. Pat. No. 3,825,442. Numerous planarization methods are also used on entire layers such as chemically etching-back an interlayer dielectric (ILD) as taught in U.S. Pat. No. 4,775,550. More recently, chemical-mechanical polishing (CMP) has been used for planarization, such as shown in U.S. Pat. Nos. 5,554,064 and 5,635,083. Another technique used to promote planarized surfaces is the fabrication of dummy features to, for example, provide more uniformed etching and deposition over the entire wafer, as discussed in U.S. Pat. No. 5,278,105.
A problem resulting from CMP is erosion of the underlayer, and is sometimes known as "dishing". Control of the uniformity and variability of dishing addressed by the present invention. An example of dishing is shown in the cross-sectional elevation view of a pair of alignment marks 10 of FIG. 1. Often during the fabrication of integrated circuits, alignment marks are fabricated in the scribe lines lying between the dies of a wafer. In some cases marks are elongated trenches fabricated in one layer of the integrated circuit to provide optical alignment for the next layer of the circuit. In FIG. 1, the example shown illustrates a pair of parallel tungsten filled trenches 10 separated by a predetermined distance. The trenches are formed in an ILD 12 such as a chemical vapor deposited, silicon dioxide (oxide) layer. The marks 10 are formed simultaneously with the fabrication of tungsten plugs of the integrated circuits in the device areas. In general the process for forming these plugs includes, following the deposition of the ILD 12, the etching of openings (vias) in the die area simultaneously with the etching of the trenches for the marks 10, the deposition of an adhesion layer 14 such as titanium nitride (TiN), and the deposition of the plug material such as tungsten. Then the tungsten and TiN layers are polished back using CMP leaving only the plugs.
As shown in FIG. 1 a nonuniform dish 15 results at the marks caused by erosion of the ILD in the proximity to the marks. This non-uniform and non-symmetric dishing is due to something sometimes referred to as the proximity effect since it results at the edge of features and is influenced by the surrounding features. Another effect, sometimes referred to as the rotational effect, describes an asymmetric erosion demonstrated in FIG. 1 by the fact that the leading edge 16 is sloped differently than the trailing edge 17 of the dish 15. This effect is particularly troublesome since alignment for the subsequent layer is made to the outer edges of the marks and the asymmetric slopes cause misalignment. This problem has been recognized, see for example, "Pattern Density Effects in Tungsten CMP," Rutten, Feeney, Cheek and Landers, 1995 ISMIC, beginning at page 419 and "CMP Overlay Metrology: Robust Performance Through Signal and Noise Improvements," Podlesny, Cusack and Redmond, SPIE Vol.8050, beginning at page 293.
One approach to the dishing problem is to segment each of the marks into a plurality of segments such as shown in "Effect of Processing on the Overlay Performance of a Wafer Stepper,"Dirksen, et al., SPIE Vol. 3050, beginning at page 102; see FIG. 10 on page 110. Additionally, this is discussed in "A CMP Compatible Alignment Strategy," Rouchouze, Darracq and Gemen, SPIE Vol. 3050, beginning at page 282.
The dishing from the CMP also occurs at the transition between the low feature density and the high feature density die areas. This is shown in FIG. 2 where feature height is plotted against horizontal distance with line 20 being the demarcation between a low density "open" area and the high density device structure. As can be seen from FIG. 2, the first several hundred microns of the device for one process has relatively high variation in heights at the transition from low to high feature density following the CMP. The dishing depth returns to an equilibrium depth further from the transition zone. These depth variations can cause portions of a subsequently formed photoresist layer to be out of the focus plane during patterning.